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Description
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 42-pin plastic SOJ and 44/50 pin plastic.
Features * Single 5V( 10 ) or 3.3V(+10%,-5%) only power supply * High speed tRAC acess time: 50/60ns * Low power dissipation - Active wode : 5V version 660/605 mW (Mas) 3.3V version 432/396 mW (Mas) - Standby mode: 5V version 1.375 mW (Mas) 3.3V version 0.54 mW (Mas) * Extended - data - out(EDO) page mode access * I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) * 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version) * 3 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
Pin Configuration 42-Pin 400mil Plastic SOJ
44-Pin 400mil Plastic TSOPII
VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC
1 2 3 4 5 6 7 8
44 43 42 41 40 39 38 37 36 35 34
VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC
VG26(V)(S)18165CJ
VG26(V)(S)18165CT
9 10 11 12 13 14 15 16 17 18 19 20 21
9 10 11
NC NC WE RAS NC NC A0 A1 A2 A3 VCC
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Description Pin Name A0-A9 Function Address inputs - Row address - Column address - Refresh address Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+5 V or + 3.3V) Ground A0-A9 A0-A9 A0-A9
DQ1~DQ16 RAS UCAS, LCAS WE OE Vcc Vss
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
Block Diagram
WE LCAS UCAS CAS
CONTROL LOGIC
DATA - IN BUFFER DQ1 . . DQ16
NO.2 CLOCK GENERATOR
DATA - OUT BUFFER OE
COLUMNADDRESS BUFFERS (10) A0 A1 A2 A3 A4 A5 A6 A7
ROW DECODER
COLUMN DECODER
REFRESH CONTROLLER
1024
SENSE AMPLIFIERS I/0 GATING REFRESH COUNTER
1024x16
A8 A9 ROW ADDRESS BUFFERS (10)
1024 x 1024 x 16 MEMORY ARRAY
1024
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
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TRUTH TABLE
FUNCTION STANDBY READ : WORD
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
ADDRESSES RAS H L L LCAS HX L L UCAS HX L H WE X H H OE X L L ROW X ROW ROW COL X COL COL High-Z Data-Out Lower Byte: Data-Out Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-Out Data-In DQS Notes
READ : LOWER BYTE
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE : UPPER BYTE (EARLY) READ WRITE PAGE-MODE READ 1st Cycle 2nd Cycle PAGE-MODE WRITE 1st Cycle 2nd Cycle PAGE-MODE READWRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE RAS-ONLY REFRESH CBR REFRESH
L
L
L
L
X
ROW
COL
L
L
H
L
X
ROW
COL
Lower Byte: Data-In Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z 4 1,2 2 2 1 1 1,2 1,2 2 1,3
L
H
L
L
X
ROW
COL
L L L L L L L LHL LHL L HL
L HL HL HL HL HL HL L L H L
L HL HL HL HL HL HL L L H L
HL H H L L HL HL H L X H
LH L L X X LH LH L X X X
ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X
COL COL COL COL COL COL COL COL COL n/a X
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS).
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
Parameter 5V Symbol VT -0.5 to + 4.6 -1.0 to + 7.0 VCC -0.5 to + 4.6 IOUT PD TOPT TSTG 50 1.0 0 to + 70 -55 to + 125 mA W
C C
Absolute Maximum Ratings
Value -1.0 to + 7.0
Unit V
Voltage on any pin relative to Vss 3.3V 5V Supply voltage relative to Vss 3.3V Short circuit output current Power dissipation Operating temperature Storage temperature
V
Recommended DC Operating Conditions
Parameter/Condition
Symbol Min
5 Volt Version Typ 5.0 Max 5.5 Min
3.3 Volt Version Typ 3.3 Max 3.6
Unit
Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs
VCC VIH VIL
4.5 2.4 -1.0
3.15 2.0 -0.3
V V V
- VCC + 1.0 0.8
- VCC + 0.3 0.8
Capacitance Ta = 25C, VCC = 5V 10 % or 3.3V(+10%,-5%), f = 1MHz
Parameter Input capacitance (Address) Input capacitance (RAS , LCAS , UCAS, OE, WE) Output capacitance (Data-in, Data-out)
Symbol CI1 CI2 CI/O
Typ -
Max 5 7 7
Unit pF pF pF
Note 1 1 1, 2
-
Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, LCAS and UCAS = VIH to disable Dout.
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 C, VCC= + 5V 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(V)(S)18165C -5 Min Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min TTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface Standby Current ICC2 Standard power version RAS, CAS Vcc -0.2V Dout = High-Z TTL interface RAS,LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS Vcc -0.2V Dout = High-Z RAS-only refresh current ICC3 RAS cycling, LCAS / UCAS = VIH tRC = min tRC = min tRC = min RAS, LCAS / UCAS cycling t RAS 100s Standby: VCC- 0.2V RAS CAS before RAS refresh: 2048 cycles / 128ms RAS,LCAS / UCAS: 0V V IL 0.2V VCC- 0.2V V IH V IH (Max) Dout = High-Z, t RAS 300ns 145 135 mA 1, 2 2 2 mA Max 145 Min -6 Max 135 mA 1, 2 Unit Notes
Low power S-version
-
2
-
2
mA
-
0.25
-
0.25
mA
1
-
1
mA
EDO page mode current CAS-before-RAS refresh current Self-refresh current (S - Version) CAS- before- RAS long refresh current (S-Version)
ICC4 ICC5 ICC8 ICC9
-
100 145 350 500
-
90 135 350 500
mA mA A A
1, 3 1, 2
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
DC Characteristics ; 5-Volt Version (Cont.) (Ta = 0 to + 70C, VCC = + 5V 10 %,VSS = 0V) VG26(V)(S)18165C -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V V IN V CC + 0.5V 0V V OUT V CC + 0.5V Dout = Disable IOH = - 5mA IOL = + 4.2mA Min -5 -5 Max 5 5 Min -5 -5 -6 Max 5 5 Unit A A V V Notes
Output high Voltage Output low voltage
2.4 -
0.4
2.4 -
0.4
Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70C, VCC = 3.3V(+10%,-5%), VSS = 0V)
Parameter
Symbol
Test Conditions
VG26(V)(S)18165C -5 Min Max 145 Min -6 Max 135
Unit
Notes
Operating current
ICC1
RAS cycling LCAS / UCAS cycling tRC = min LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC -0.2V Dout = High-Z
-
mA
1, 2
Low power S-version
ICC2
-
0.5
-
0.5
mA
-
0.15
-
0.15
mA
Standby Current
Standard power version
LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC -0.2V Dout = High-Z
-
2
-
2
mA
-
0.5
-
0.5
mA
RAS- only refresh current
ICC3
RAS cycling LCAS / UCAS = VIH tRC = min tPC = min tRC = min RAS, LCAS / UCAS cycling t RASS 100s Standby: VCC- 0.2V RAS CAS before RAS refresh: 2048 cycles / 128ms RAS, LCAS / UCAS : 0V V IL 0.2V VCC- 0.2V V IH VIH (max) Dout = High-Z, t RAS 300ns
-
145
-
135
mA
1, 2
EDO page mode current CAS- before- RAS refresh current Self- refresh current (S-Version) CAS- before- RAS long refresh current (S-Version)
ICC4 ICC5 ICC8 ICC9
-
100 145 250 300
-
90 135 250 300
mA mA A A
1, 3 1, 2
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
DC Characteristics ; 3.3 - Volt Version (Cont.) (Ta = 0 to 70C, VCC= 3.3V(+10%,-5%), VSS= 0V) VG26(V)(S)18165C -5 Parameter Input leakage current Output leakage current Output high Voltage Output low voltage Symbol ILI ILO VOH VOL Test Conditions 0V Vin VCC + 0.3V 0V Vout VCC + 0.3V Dout = Disable IOH = -2mA IOL = +2mA 2.4 0.4 2.4 0.4 V V Min -5 -5 Max 5 5 Min -5 -5 -6 Max 5 5 A A Unit Notes
Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
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AC Characteristics
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
(Ta = 0 to + 70C, Vcc = 5V 10 % or 3.3V(+10%,-5%), Vss = 0V) *1, *2, *3, *4, *5
Test conditions * Output load: two TTL Loads and 50pF (VCC = 5.0V 10 %) one TTL Load and 30pF (VCC =3.3V(+10%,-5%) ) * Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V(+10%,-5%)) * Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5V 10 %,3.3V(+10%,-5%) )
Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 18165C -5 Parameter Random read or write cycle time RAS precharge time LCAS / UCAS precharge time in normal mode RAS pulse width LCAS / UCAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to LCAS / UCAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time LCAS / UCAS hold time LCAS / UCAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period Refresh period (S- Version) LCAS / UCAS to output in Low- Z LCAS / UCAS delay time from Din OE delay time from Din
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Unit
Notes
-6 Max Min 104 40 10 Max ns ns ns
Symbol tRC tRP tCPN tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tREF tCLZ tDZC tDZO
Min 84 30 10
50 8 0 8 0 8 12 10 25 8 38 5 12 1 0 0 0
Rev.4
10000 10000 37 25 50 16 128 -
60 10 0 10 0 10 14 12 30 10 40 5 15 1 0 0 0
10000 10000 45 30 50 16 128 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns
6 7
8
9 10
11
12
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Read Cycle
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
VG26(V)(S)18165C -5 Parameter Access time from RAS Access time from LCAS / UCAS Access time from column address Access time from OE Read command setup time Read command hold time to LCAS / UCAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ Min 0 0 10 0 0 Max 50 13 25 12 12 12 Min 0 0 10 0 0 -6 Max 60 15 30 15 15 15
Unit
Notes
ns ns ns ns ns ns ns ns ns
13 14, 15 15, 16
8 11, 17 17 18 18
Write Cycle VG26(V)(S)18165C -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to LCAS / UCAS lead time Data-in setup time Data-in hold time WE to Data-in delay Symbol tWCS tWCH tWP tRWL tCWL tDS tDH tWED Min 0 8 8 13 8 0 8 10 Max Min 0 10 10 15 10 0 10 10 -6 Max ns ns ns ns ns ns ns ns 20 21 21 8, 19 Unit Notes
Read- Modify- Write Cycle VG26(V)(S) 18165C -5 Parameter Read-modify- write cycle time RAS to WE delay time LCAS / UCAS to WE dealy time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 108 64 26 39 8 Max Min 133 77 32 47 10 -6 Max ns ns ns ns ns 19 19 19 Unit Notes
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Refresh Cycle
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
VG26(V)(S)18165C -5 Parameter LCAS / UCAS setup time (CBR refresh) LCAS / UCAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) LCAS / UCAS hold time (CBR self refresh) WE setup time WE hold time tWSR tWHR 0 10 0 10 ns ns Symbol tCSR tCHR tRPC tRASS tRPS tCHS Min 5 8 5 100 90 -50 Max Min 5 10 5 100 110 -50 -6 Max Unit ns ns ns s ns ns 11 8 Notes
EDO Page Mode Cycle VG26(V)(S)18165C -5 Parameter EDO page mode cycle time EDO page mode LCAS / UCAS precharge time EDO page mode RAS pulse width Access time from LCAS / UCAS precharge RAS hold time from LCAS / UCAS precharge OE high hold time from LCAS / UCAS high OE high pulse width Data output hold time after LCAS / UCAS low Output disable delay from WE WE pulse width for output disable when LCAS / UCAS high Symbol tPC tCP tRASP tCPA tCPRH tOEHC tOEP tCOH tWHZ tWPZ Min 20 10 50 30 5 10 4 3 7 Max 105 30 10 Min 25 10 60 35 5 10 4 3 7 -6 Max 105 35 10 Unit ns ns ns ns ns ns ns ns ns ns 22 11, 15 Notes
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
EDO Page Mode Read Modify Write Cycle VG26(V)(S)18165C -5 Parameter EDO page mode read- modify- write cycle LCAS / UCAS precharge to WE delay time EDO page mode read- modify- write cycle time Symbol tCPW tPRWC Min 45 56 Max Min 55 68 -6 Max Unit ns ns Notes 11
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Notes :
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
1. AC measurements assume tT = 2ns. 2. An initial pause of 100 s is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 6. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle. 7. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 8. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS . 9. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 10. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 11. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS . 12. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 13. Assumes that tRCD
tRCD(max) and tRAD
tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that t RCD
t RCD (max) and t RAD t RAD (max). t RAD (max).
15. Access time is determined by the maximum of tAA, tCAC, tCPA. 16. Assumes that t RCD t RCD (max) and t RAD
17. Either tRCH or tRRH must be satisfied for a read cycle. 18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). tOFF is determined by the later rising edge of RAS or CAS. 19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t RWD t CWD
t RWD (min),
t CWD (min),
t AWD
t AWD (min) and
t CPW
t CPW (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 20. tCWL shall be satisfied by both LCAS and UCAS. 21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 22. tRASP defines RAS pulse width in EDO page mode cycles.
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
Timing Waveforms * Word Read Cycle
t RC t RAS t RP
RAS
t CRP t CSH t RCD t T t RSH t CAS t CPN
UCAS LCAS
t RAD t RAL
t ASR
t RAH
t ASC
t CAH
ADDRESS
Row
Column
t RRH
t RCS
t RCH
WE
OE
t OEA t CAC t AA t RAC t OEZ t OFF
DQ1~DQ16
t CLZ
DOUT
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Byte Read Cycle
t RC t RAS t RP
RAS
t CSH t RCD t T t RSH t CAS
t CRP
UCAS (or LCAS)
LCAS (or UCAS)
t RAD t ASR t RAH Row t ASC Column t RAL t CAH
ADDRESS
tRRH
t RCS
t RCH
WE
OE
t OEA t CAC t AA t RAC t OEZ t OFF
DQ9~DQ16 (or DQ1~DQ8)
DOUT t CLZ
DQ1~DQ8 (or DQ9~DQ16)
High-Z
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Word Early Write Cycle
t RC t RAS t RP
RAS
t CSH t RCD t T t RSH t CAS
t CRP
UCAS LCAS
t RAD t RAL
t ASR
t RAH Row
t ASC
t CAH Column
ADDRESS
t WCS
t WCH
WE
t DS
t DH
DQ1~DQ16
DIN
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Byte Early Write Cycle
t RC t RAS t RP
RAS
t CSH t RCD t T t RSH t CAS
t CRP
LCAS (or UCAS)
LCAS (or UCAS)
t RAD t ASR t RAH Row t ASC t RAL t CAH Column
ADDRESS
t WCS
t WCH
WE
tDS
t DH
DQ9~DQ16
DIN
DQ1~DQ8
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Word Delayed Write Cycle
t RC t RAS t RP
RAS
t CSH t RCD t T t RSH t CAS
t CRP
t CPN
UCAS LCAS
t ASR
t RAH
t ASC
t CAH
ADDRESS
Row
Column
t CWL t RWL t RCS t WP
WE
t OEH
t OED
OE
t DS
t DH
DQ1~DQ16
OPEN
DIN
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Byte Delayed Write Cycle
t RC t RAS t RP
RAS
t CSH t RCD t T t RSH t CAS
t CRP
LCAS (or UCAS)
LCAS (or UCAS)
t ASR t RAH t ASC t CAH
ADDRESS
Row
Column
tCWL t RCS
t RWL t WP
WE
t OEH
tOED
OE
t DS
t DH
DQ9~DQ16 (or DQ1~DQ8)
OPEN
DIN
DQ1~DQ8 (or DQ9~DQ16)
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Word Read-Modify-Write Cycle
t RWC t RAS t RP
RAS
t T
t RCD
t CAS
t CRP t CPN
UCAS LCAS
t RAD t ASR t ASC
t RAH
t CAH
ADDRESS
Row
Column t CWD t AWD t RWD
t RCS
t CWL t RWL t WP
WE
t DS
t DH
DQ1~DQ16
OPEN
D in
t OED
t OEH
OE
t OEA t CAC t AA t RAC
t OEZ
DQ1~DQ16
DOUT
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* EDO Page Mode Word Read-Modify-Write Cycle
t RASP tCPRH t RP
RAS
t T t RCD t CAS t CP t PRWC t CAS tCP t CAS
t CRP
UCAS LCAS
t RAD t ASR t RAH t ASC t CAH t ASC t CAH
t RAL t ASC t CAH
ADDRESS
Row
Column 1 Column 1 t RWD t AWD t CWD t CWL
Column 2 t CPW t AWD t CWD t CWL
Column N t t CWL CPW t AWD t CWD
t RWL
t RCS
WE
WE
t RCS t WP t DS tDH t WP t DS t DH t WP t DS t DH OPEN
DQ1~DQ16
OPEN
Din 1
OPEN
Din 2
Din N
tDZO
tOED tOEH
tOED
tOEH
tOED
tOEH
OE
tOEA tCAC tRAC tAA t OEZ t OEA tCAC tAA tCPA tOEZ tCAC tAA tCPA tOEZ tOEA
DQ1~DQ16
DOUT 1
DOUT 2
DOUT N
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* EDO Page Mode Word Read-Early-Write Cycle
t RASP t CPRH t RP
RAS
t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN
UCAS LCAS
t CSH t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAL t RAL t CAH
ADDRESS
Row
Column 1
Column 2
Column N
Row
t RCS
t RCH
t WCS t WCH
WE
WE
tOEA t WED
OE
OE
tRAC tAA tCAC tCPA tAA tCAC tCOH
OPEN Data Output 1 Data Output 2 Data Intput N
tWHZ tDH tDS
DQ1~DQ16
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VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Read Cycle with WE Controlled Disable
RAS
t CSH t RCD t T t CAS
UCAS LCAS
t RAD t ASR t RAH t ASC t CAH
ADDRESS
Row
Column
t RCS
t RCH
t WPZ
WE
t WHZ t OED
OE
t DS tOEA tCAC tAA tRAC tOEZ
DQ1~DQ16
tCLZ
DOUT
Document:1G5-0158
Rev.4
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VIS
RAS
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
t RC t RAS t RP
RAS - Only Refresh Cycle
tT t CRP tRPC tCRP
UCAS LCAS
tASR
tRAH
ADDRESS
Row
tOFF OPEN
DQ1~DQ16
CAS-Before-RAS Refresh Cycle
tRC tRP
tRC tRP tRAS t RP
RAS
tRAS
tT tRPC t CSR t CHR
tRPC tCSR tCHR
tCRP
UCAS LCAS
tWSR tWHR tWSR tWHR
WE
tOFF OPEN
DQ1~DQ16
Document:1G5-0158
Rev.4
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VIS
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
* Hidden Refresh Cycle
t RC tRAS
(READ)
t RC t RP tRAS
(REFRESH)
t RC t RP tRAS
(REFRESH)
tRP
RAS
tT
t CHR tRSH tRCD tCAS
tCRP
UCAS LCAS
t RAD t ASR t RAH tASC t RAL tCAH
ADDRESS
Row
Column
tRRH t RCS tRCH
WE
OE
tORD t OEA t CAC t AA t RAC t OEZ t OFF t OFF
DQ1~DQ16
D OUT
Document:1G5-0158
Rev.4
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VIS
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
Ordering information Part Number VG26(V)18165CJ-4 VG26(V)18165CJ-5 VG26(V)18165CJ-6 VG26(V)(S)18165CT-4 VG26(V)(S)18165CT-5 VG26(V)(S)18165CT-6 Access time 50 ns 60 ns Package 400mil 42-Pin Plastic SOJ 400mil 50/44-Pin Plastic TSOP
VG26(V)(S)18165CJ-5 * VG
* 26 *V *S * 18165 *C
* VIS Memory Product * Technology * 3.3V Version * Self refresh * Device Type and Configuation * Revision * Package Type (J : SOJ, T : TSOP II)
* Speed (5 : 50 ns, 6 : 60 ns)
*J
*5
Document:1G5-0158
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VIS
DIM A A1 A2 b b1 b2 c c1 e D E E1 E2 R1
VG26(V)(S)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM
D
MILLIMETERS MIN. NOM. MAX. 3.25 3.51 3.76 2.08 ----2.79 REF. --0.38 0.51 --0.38 0.46 0.66 0.71 0.81 0.18 --0.33 0.18 0.20 0.28 1.27 BASIC 27.18 27.31 27.43 11.05 11.18 11.30 10.03 10.16 10.29 9.40 BASIC 0.76 0.89 1.02 3 --16
INCHES MIN. NOM. MAX. 0.128 0.138 0.148 0.082 ----0.110 REF. --0.015 0.020 --0.015 0.018 0.026 0.028 0.032 0.007 --0.013 0.007 0.008 0.011 0.050 BASIC 1.070 1.075 1.080 0.435 0.440 0.445 0.395 0.400 0.405 0.370 BASIC 0.040 0.030 0.035 16 3 ---
42
22
b b1
c1 E1 E
c
BASE METAL WITH PLATING
SECTION B-B
1 21
0.025" MIN. A2
NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025) BELOW b2 MIN.
A b2 b e 0.007" M 0.004"
B A1 E2
B
RAD R1 SEATING PLANE
A A1 A2 b b1 c c1 D ZD e E E1 L R R1
RA D
R1
DIM
MILLIMETERS MIN. NOM. MAX. ----1.20 0.05 --0.15 1.05 0.95 1.00 0.45 0.30 --0.40 0.30 --0.21 0.12 --0.16 0.11 --20.82 20.95 21.08 0.875 BASIC 0.80 BASIC 11.56 11.76 11.96 10.03 10.16 10.29 0.40 0.50 0.60 0.11 --0.25 0.11 -----
INCHES MIN. NOM. MAX. ----- 0.047 0.002 --- 0.006 0.037 0.039 0.041 --- 0.018 0.012 --- 0.016 0.012 --- 0.008 0.005 --- 0.006 0.0045 0.820 0.825 0.830 0.0344 BASIC 0.0315 BASIC 0.455 0.463 0.471 0.395 0.400 0.405 0.016 0.020 0.024 --0.010 0.004 0.004 -----
44
34
33
23
A2
D RA
R
B
E1 A1
B DETAIL A
b
L
0~5
1
11
D
12
22
b1
SECTION B-B
c1
BASE METAL WITH PLATING
DETAIL A
NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
ZD
A
b
4-1.60 REF.
40-e SEATING PLANE 0.100(0.004)
E
Document:1G5-0158
Rev.4
c
Page 28
c

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